Title: Theory / Unimportant / CS / Hardware / Intel / manual{ / Architecture
Tags: fromMath mathToDef mathToSee récupéré

Name: Modes of operations
Definition: What determines which instructions and architectural features are accessible.
Page: 1
Chapter: 3

Question: Native state (mode) of the processor is:
Answer: protected mode.
Page: 1
Chapter: 3

Name: Execution environment
Definition: Ressources allowed to a program/task for executing instructions and for storing code, data, and state information.
Page: 2
Chapter: 3

Q: -[...]
-[...]
-[...]
A: Protected mode; Real-address mode; System management mode
Page: 1
Chapter: 3
Name: The IA-32 modes

Q: -[...]
-[...]
A: Compatibility mode; 64-bit mode
Page: 1
Chapter: 3
Section: 1.1
Name: The IA-32e modes

-adress space,
-Basic program execution registers,
-x87 FPU registers,
-MMX registers,
-XMM registers,
-YMM registers,
-Bounds registers,
-BNDCFGU and BNDSTATUS,
-Stack
Page: 2
Chapter: 3
Name: Basic execution environment

-Basic execution environment,
-I/O ports,
-Controls registers,
-Memory management registers,
-Debug registers,
-Memory type range registers,
-Machine specific registers,
-Machine check registers,
-Performance monitoring counters
Page: 2
Chapter: 3
Section: 4
Name: Execution environment of the IA-32 architecture

Q: [...].
A: basic integer arithmetic on byte,word, and doubleword integers, handle program flow control, operate on bit and byte strings, and address memory
Page: 2
Chapter: 3
Name: Basic program execution registers
-The eight general-purpose registers,
-the six segment registers,
-the EFLAGS register and
-the EIP (instruction pointer) register

Name: x87 FPU registers
Definition: An execution environment for operating on single-precision, double-precision, and double extended-precision floating-point values, word integers, doubleword integers, quadword integers, and binary coded decimal (BCD) values.
Page: 2
Chapter: 3
Extra: The eight x87 FPU data registers, the x87 FPU control register, the status register, the
x87 FPU instruction pointer register, the x87 FPU operand (data) pointer register, the x87 FPU tag register, and
the x87 FPU opcode registe

Name: MMX registers
Definition: Execution of single-instruction, multiple-data (SIMD) operations on 64-bit packed byte, word, and doubleword integers.
Page: 2
Chapter: 3
Extra: The eight MMX registers

Name: XMM registers
Definition: Execution SIMD operations on 128-bit packed single-precision and double-precision floating-point values and on 128-bit packed byte, word, doubleword, and quadword integers.
Page: 2
Chapter: 3
Extra: The eight XMM registers and the MXCSR register

Q: Store [...].
They support [...].
A: the lower and upper bounds (64 bits each) associated with the pointer to a memory buffer; execution of the Intel MPX instructions
Page: 2
Chapter: 3
Name: Bounds registers

Name: YMM registers
Definition: A register which support execution of 256-bit SIMD operations on 256-bit packed single-precision and double-precision floating-point values and on 256-bit packed byte, word, doubleword, and quadword integers.
Page: 2
Chapter: 3

Name: BNDCFGU
Definition: Configures user mode MPX operations on bounds checking.
Page: 2
Chapter: 3

Name: DNDSTATUS
Definition: Provides additional information on the #BR caused by an MPX operation.
Page: 2
Chapter: 3

Name: Stack
Definition: Support procedure or subroutine calls and the passing of parameters between procedures or subroutines.
Page: 4
Chapter: 3
Section: 2

Name: Control registers
Definition: Registers which determine the operating mode of the processor and the characteristics of the currently executing task.
Page: 4
Chapter: 3
Section: 2
Notation: CR0, CR1, CR2, CR3, CR4

Name: Memory management registers
Definition: A register which specifies the locations of data structures used in protected mode memory management.
Page: 4
Chapter: 3
Section: 2
Extra: The GDTR, IDTR, task register, and LDTR

Name: Debug registers
Definition: Monitoring of the processor’s debugging operations.
Page: 4
Chapter: 3
Section: 2
Notation: DR0 through DR7

Name: Memory type range registers
Definition: Assign memory types to regions of memory.
Page: 4
Chapter: 3
Section: 2

Name: Machine check registers
Definition: A set of control, status, and error-reporting MSRs that are used to detect and report on hardware (machine) errors.
Page: 4
Chapter: 3
Section: 2

Name: Performance monitoring counters
Definition: Allow processor performance events to be monitored.
Page: 4
Chapter: 3
Section: 2

Definition: nor

Definition: nand

Definition: not
Context: circuits

Definition: xor

Definition: or

Definition: and