Title: Theory / Unimportant / CS / Hardware / Structured computer organization - Tanenbaum, Austin / 2 Computer Systems Organisation
Tags: examplesSwitchExample1 récupéré

Name: (kilo, , ...) bit per seconds
Page: 49
Chapter: 1
Section: 5
Abbreviation: (k,m,...)bps&nbsp
Extra: Other abbreviations are given in "constant" deck

Name: Bus
Definition: Collection of parallel wires for transmitting address, data, control signals
Page: 55
Chapter: 2
Section: 1

Name: Program counter
Definition: Points to the next instruction to be fetched for execution
Page: 56
Chapter: 2
Section: 1
Abbreviation: PC register

Name: Instruction Register
Definition: Register which holds the instruction currently being executed.
Page: 56
Chapter: 2
Section: 1
Context: microprocessor
Abbreviation: IR
Typ: Register

Name: A Register-Memory operation
Definition: An instruction which allow memory words to be fetched into register.
Page: 57
Chapter: 2
Section: 1

Name: A Register-Register operation
Definition: An instruction which takes the content of register(s), do some action on it, and store them back in a register.
Page: 57
Chapter: 2
Section: 1

Name: A data path cycle
Definition: The process of running two operands through the ALU and storing the result
Page: 58
Chapter: 2
Section: 1

Name: fetch-decode-execute cycle
Definition: 1. Fetch the next instruction from memory into the instruction register.
2. Change the program counter to point to the following instruction.
3. Determine the type of instruction just fetched.
4. If the instruction uses a word in memory, determine where it is.
5. Fetch the word, if needed, into a CPU register.
6. Execute the instruction.
7. Go to step 1 to begin executing the following instruction.
Page: 58
Chapter: 2
Section: 1.2

Question: Why to simulates hardware with software ?
Answer: Can use simpler, less expensive hardware, test design, and replicate program for hardware we don't have.
Page: 59
Chapter: 2
Section: 1.2

Question: Why one use more complex instruction set ?
Answer: It leads to faster program
Page: 60
Chapter: 2
Section: 1.2
Example: Array access, floating point arithmetic

Question: How to offer the same set of instructions with different quality of hardware ?
Answer: On cheaper hardware, simulate missing instructions.
Page: 60
Chapter: 2
Section: 1.2

Name: Microinstruction
Definition: An instruction of the processor, used to interpret an instruction of the "control" language.
Page: 62
Chapter: 2
Section: 1.2

Name: Control store
Definition: hold the interpreters
Page: 61
Chapter: 2
Section: 1.2
Typ: Fast read-only memory

Question: What matters, at hardware level, concerning the speed of execution of program ?
Answer: Number of instructions which can be started simultaneously.
Page: 62
Chapter: 2
Section: 1.3

Name: Issuing an instruction
Definition: Starting an instruction
Page: 62
Chapter: 2
Section: 1.3

Name: Reduced Instruction Set Computer
Definition: Small set of instruction, executed in one cycle of data path.
Page: 62
Chapter: 2
Section: 1.3
Abbreviation: RISC

Name: Complex Instruction Set Computer
Page: 62
Chapter: 2
Section: 1.3
Abbreviation: CISC

Name: RISC design principles
Definition: All Instructions Are Directly Executed by Hardware
Page: 63, 64
Chapter: 2
Section: 1.4
Definition2: Maximize the Rate at Which Instructions Are Issued
Conjdef: Simultaneously
Definition3: Instructions Should Be Easy to Decode
Definition4: Only Loads and Stores Should Reference Memory
Definition5: Provide Plenty of Registers

Definition: Microprocessor without Interlocked Pipeline STages
Page: 64
Chapter: 2
Section: 1.4
Notation: MIPS
Definition2: Millions of Instruction Per Second

Name: Instruction-level parallelism
Definition: Parallelism exploited within individual instructions to get more instructions/sec out of the machine.
Page: 65
Chapter: 2
Section: 1.5

Name: Processor-level parallelism
Definition: Having multiple CPUs work together on the same problem.
Page: 65
Chapter: 2
Section: 1.5

Name: Prefetch buffer
Definition: Buffer to save instructions which will probably be executed soon.
Page: 65
Chapter: 2
Section: 1.5

Name: Pipeline
Definition: The fact that instruction execution is divided into many (often a dozen or more) parts, each one handled by a dedicated piece of hardware, all of which can run in parallel.
Page: 65
Chapter: 2
Section: 1.5
Context: Instruction-level parallelism

Name: Stage
Definition: One unit of a pipeline.
Page: 66
Chapter: 2
Section: 1.5
Context: Instruction-level parallelism

Question: Having longer pipeline means that
Answer: the latency increase
Page: 67
Chapter: 2
Section: 1.5
Answer2: the bandwidth increase

Name: Latency of a processor
Definition: How long it takes to execute an instruction
Page: 67
Chapter: 2
Section: 1.5

Name: The bandwidth of the processor P
Definition: How many MIPS the CPU P has
Page: 67
Chapter: 2
Section: 1.5
Variables: P a processor

Name: Dual pipeline
Definition: Having multiple pipelines working in parallel.
Page: 67
Chapter: 2
Section: 1.5

Name: u pipeline
Definition: A pipeline, in Pentium, which could any instruction.
Page: 68
Chapter: 2
Section: 1.5
Context: Pentium processor from 486

Name: v pipeline
Definition: A pipeline, in Pentium, which could execute simple instruction.
Page: 68
Chapter: 2
Section: 1.5
Context: Pentium processor, starting at 486

Name: A superscalar processor
Definition: A processor which issue multiple instructions in a single clock cycle
Page: 68
Chapter: 2
Section: 1.5

Name: Single Instruction-stream Multiple Data-stream
Definition: A large number of identical processors that perform the same sequence of instructions on different sets of data.
Page: 70
Chapter: 2
Section: 1.6
Abbreviation: SIMD

Name: Vector processor
Definition: Processor performing its actions on single, heavily pipelined functional unit.
Page: 71
Chapter: 2
Section: 1.6

Name: Vector registor
Definition: A sequence of registor, such that a single operation (fetch, write, add...) act on every elements of the sequence.
Page: 71
Chapter: 2
Section: 1.6

Name: Multiprocessor
Definition: A system with more than one CPU sharing a common memory
Page: 72
Chapter: 2
Section: 1.6

Name: Tightly coupled CPU
Definition: CPU which are able to interact closely.
Page: 72
Chapter: 2
Section: 1.6

Name: Multicomputers
Definition: Systems consisting of large numbers of interconnected computers, each having its own private memory, but no common memory
Page: 73
Chapter: 2
Section: 1.6

Smaller0: \(I_1\) and \(I_2\) must not conflict over resource usage
Greater0: \(I_1\) and \(I_2\) can be run in parallel
Page: 67
Chapter: 2
Section: 1.5
Variables: \(I_1\), \(I_2\) two instructions
Smaller1: neither instruction must depend on the result of the other